 # Project Setup Variables
  set PROJ_NAME "myproj"
  set PART "xc7a200tfbg676-2"
  set BOARD "xilinx.com:ac701:part0:1.3"
  #set PART "xcku040-ffva1156-2-e"
  #set BOARD "xilinx.com:kcu105:part0:1.0"
  #set PART "xc7z045ffg900-2"
  #set BOARD "xilinx.com:zc706:part0:1.1"

  # Create the project - Builds project in the current directory.
  create_project $PROJ_NAME ./$PROJ_NAME -part $PART -force
  set_property board_part $BOARD [current_project]

# Create synthesis/implementation/simulation fileset
add_files -fileset sources_1 -norecurse {../../par/xilinx_vivado/define.v}
add_files -fileset sources_1 -norecurse {../../src/rtl/top/mac_top.v}
add_files -fileset sources_1 -norecurse {../../src/rtl/tx/tx_top.v}
add_files -fileset sources_1 -norecurse {../../src/rtl/tx/gmii2rgmii.v}
add_files -fileset sources_1 -norecurse {../../src/rtl/tx/tx_gearbox.v}
add_files -fileset sources_1 -norecurse {../../src/rtl/rx/rx_top.v}
add_files -fileset sources_1 -norecurse {../../src/rtl/rx/rgmii2gmii.v}
add_files -fileset sources_1 -norecurse {../../src/rtl/rx/rx_gearbox.v}

# Create simulation only fileset
set_property SOURCE_SET sources_1 [get_filesets sim_1]

add_files -fileset sim_1 -norecurse {src/testbench/top_bench.v}
add_files -fileset sim_1 -norecurse {../../sim/top/bfm/phy_rgmii_bfm.v}
add_files -fileset sim_1 -norecurse {../../sim/top/phy_rgmii_rx_source.pcap}

# Set individual file properties
set_property is_global_include true [get_files  ../../par/xilinx_vivado/define.v]

set_property used_in_synthesis      false [get_files  src/testbench/top_bench.v]
set_property used_in_synthesis      false [get_files  ../../sim/top/bfm/phy_rgmii_bfm.v]
set_property used_in_implementation false [get_files  src/testbench/top_bench.v]
set_property used_in_implementation false [get_files  ../../sim/top/bfm/phy_rgmii_bfm.v]

set_property file_type {Data Files} [get_files  ../../sim/top/phy_rgmii_rx_source.pcap]
set_property used_in_synthesis false [get_files  ../../sim/top/phy_rgmii_rx_source.pcap]

# Add IP AXI interface fileset
add_files -fileset sources_1 -norecurse {ip_repo/MiniMAC_1Ge_AXI_1.0/hdl/MiniMAC_1Ge_AXI_v1_0.v}
add_files -fileset sources_1 -norecurse {ip_repo/MiniMAC_1Ge_AXI_1.0/hdl/MiniMAC_1Ge_AXI_v1_0_M00_AXIS.v}
add_files -fileset sources_1 -norecurse {ip_repo/MiniMAC_1Ge_AXI_1.0/hdl/MiniMAC_1Ge_AXI_v1_0_S00_AXIS.v}
add_files -fileset sources_1 -norecurse {ip_repo/MiniMAC_1Ge_AXI_1.0/hdl/MiniMAC_1Ge_AXI_v1_0_S00_AXI.v}

# Set Top-level design unit
set_property top design_1_wrapper [get_filesets sources_1]
set_property top top_bench [get_filesets sim_1]

### Create block design
##create_bd_design "design_1"
### Reference RTL module from sources_1
##create_bd_cell -type module -reference MiniMAC_1Ge_AXI_v1_0 MiniMAC_1Ge_AXI_v1_0_0
##update_module_reference {design_1_MiniMAC_1Ge_AXI_v1_0_0_0 design_1_MiniMAC_1Ge_AXI_v1_0_0_1}

# Rebuild block design
source ./src/sys_rtl/design_1_bd.tcl
save_bd_design
validate_bd_design

# Add top-level block design wrapper
add_files -norecurse ./src/sys_rtl/design_1_wrapper.v

# Update compile order
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
save_bd_design

#reset_run synth_1
#reset_run impl_1

#launch_runs synth_1 -jobs 1
#wait_on_run synth_1

#launch_runs impl_1 -jobs 1
#wait_on_run impl_1

#launch_runs impl_1 -to_step write_bitstream
#wait_on_run impl_1

